505 lines
13 KiB
C
505 lines
13 KiB
C
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/*
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mcp_can_dfs.h
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2012 Copyright (c) Seeed Technology Inc. All right reserved.
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Author:Loovee (loovee@seeed.cc)
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2014-1-16
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Contributor:
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Cory J. Fowler
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Latonita
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Woodward1
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Mehtajaghvi
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BykeBlast
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TheRo0T
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Tsipizic
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ralfEdmund
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Nathancheek
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BlueAndi
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Adlerweb
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Btetz
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Hurvajs
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xboxpro1
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ttlappalainen
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The MIT License (MIT)
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Copyright (c) 2013 Seeed Technology Inc.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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#ifndef _MCP2515DFS_H_
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#define _MCP2515DFS_H_
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#include <Arduino.h>
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#include <SPI.h>
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#include <inttypes.h>
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// if print debug information
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#ifndef DEBUG_EN
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#define DEBUG_EN 1
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#endif
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// Begin mt
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#define TIMEOUTVALUE 50
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#define MCP_SIDH 0
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#define MCP_SIDL 1
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#define MCP_EID8 2
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#define MCP_EID0 3
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#define MCP_TXB_EXIDE_M 0x08 // In TXBnSIDL
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#define MCP_DLC_MASK 0x0F // 4 LSBits
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#define MCP_RTR_MASK 0x40 // (1<<6) Bit 6
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#define MCP_RXB_RX_ANY 0x60
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#define MCP_RXB_RX_EXT 0x40
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#define MCP_RXB_RX_STD 0x20
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#define MCP_RXB_RX_STDEXT 0x00
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#define MCP_RXB_RX_MASK 0x60
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#define MCP_RXB_BUKT_MASK (1<<2)
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// Bits in the TXBnCTRL registers.
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#define MCP_TXB_TXBUFE_M 0x80
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#define MCP_TXB_ABTF_M 0x40
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#define MCP_TXB_MLOA_M 0x20
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#define MCP_TXB_TXERR_M 0x10
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#define MCP_TXB_TXREQ_M 0x08
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#define MCP_TXB_TXIE_M 0x04
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#define MCP_TXB_TXP10_M 0x03
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#define MCP_TXB_RTR_M 0x40 // In TXBnDLC
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#define MCP_RXB_IDE_M 0x08 // In RXBnSIDL
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#define MCP_RXB_RTR_M 0x40 // In RXBnDLC
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#define MCP_STAT_TX_PENDING_MASK (0x54)
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#define MCP_STAT_TX0_PENDING (0x04)
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#define MCP_STAT_TX1_PENDING (0x10)
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#define MCP_STAT_TX2_PENDING (0x40)
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#define MCP_STAT_TXIF_MASK (0xA8)
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#define MCP_STAT_TX0IF (0x08)
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#define MCP_STAT_TX1IF (0x20)
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#define MCP_STAT_TX2IF (0x80)
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#define MCP_STAT_RXIF_MASK (0x03)
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#define MCP_STAT_RX0IF (1<<0)
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#define MCP_STAT_RX1IF (1<<1)
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#define MCP_EFLG_RX1OVR (1<<7)
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#define MCP_EFLG_RX0OVR (1<<6)
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#define MCP_EFLG_TXBO (1<<5)
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#define MCP_EFLG_TXEP (1<<4)
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#define MCP_EFLG_RXEP (1<<3)
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#define MCP_EFLG_TXWAR (1<<2)
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#define MCP_EFLG_RXWAR (1<<1)
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#define MCP_EFLG_EWARN (1<<0)
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#define MCP_EFLG_ERRORMASK (0xF8) // 5 MS-Bits
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// Define MCP2515 register addresses
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#define MCP_RXF0SIDH 0x00
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#define MCP_RXF0SIDL 0x01
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#define MCP_RXF0EID8 0x02
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#define MCP_RXF0EID0 0x03
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#define MCP_RXF1SIDH 0x04
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#define MCP_RXF1SIDL 0x05
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#define MCP_RXF1EID8 0x06
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#define MCP_RXF1EID0 0x07
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#define MCP_RXF2SIDH 0x08
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#define MCP_RXF2SIDL 0x09
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#define MCP_RXF2EID8 0x0A
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#define MCP_RXF2EID0 0x0B
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#define MCP_BFPCTRL 0x0C
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#define MCP_TXRTSCTRL 0x0D
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#define MCP_CANSTAT 0x0E
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#define MCP_CANCTRL 0x0F
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#define MCP_RXF3SIDH 0x10
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#define MCP_RXF3SIDL 0x11
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#define MCP_RXF3EID8 0x12
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#define MCP_RXF3EID0 0x13
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#define MCP_RXF4SIDH 0x14
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#define MCP_RXF4SIDL 0x15
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#define MCP_RXF4EID8 0x16
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#define MCP_RXF4EID0 0x17
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#define MCP_RXF5SIDH 0x18
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#define MCP_RXF5SIDL 0x19
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#define MCP_RXF5EID8 0x1A
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#define MCP_RXF5EID0 0x1B
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#define MCP_TEC 0x1C
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#define MCP_REC 0x1D
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#define MCP_RXM0SIDH 0x20
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#define MCP_RXM0SIDL 0x21
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#define MCP_RXM0EID8 0x22
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#define MCP_RXM0EID0 0x23
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#define MCP_RXM1SIDH 0x24
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#define MCP_RXM1SIDL 0x25
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#define MCP_RXM1EID8 0x26
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#define MCP_RXM1EID0 0x27
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#define MCP_CNF3 0x28
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#define MCP_CNF2 0x29
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#define MCP_CNF1 0x2A
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#define MCP_CANINTE 0x2B
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#define MCP_CANINTF 0x2C
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#define MCP_EFLG 0x2D
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#define MCP_TXB0CTRL 0x30
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#define MCP_TXB0SIDH 0x31
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#define MCP_TXB1CTRL 0x40
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#define MCP_TXB1SIDH 0x41
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#define MCP_TXB2CTRL 0x50
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#define MCP_TXB2SIDH 0x51
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#define MCP_RXB0CTRL 0x60
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#define MCP_RXB0SIDH 0x61
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#define MCP_RXB1CTRL 0x70
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#define MCP_RXB1SIDH 0x71
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#define MCP_TX_INT 0x1C // Enable all transmit interrup ts
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#define MCP_TX01_INT 0x0C // Enable TXB0 and TXB1 interru pts
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#define MCP_RX_INT 0x03 // Enable receive interrupts
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#define MCP_NO_INT 0x00 // Disable all interrupts
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#define MCP_TX01_MASK 0x14
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#define MCP_TX_MASK 0x54
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// Define SPI Instruction Set
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#define MCP_WRITE 0x02
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#define MCP_READ 0x03
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#define MCP_BITMOD 0x05
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#define MCP_LOAD_TX0 0x40
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#define MCP_LOAD_TX1 0x42
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#define MCP_LOAD_TX2 0x44
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#define MCP_RTS_TX0 0x81
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#define MCP_RTS_TX1 0x82
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#define MCP_RTS_TX2 0x84
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#define MCP_RTS_ALL 0x87
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#define MCP_READ_RX0 0x90
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#define MCP_READ_RX1 0x94
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#define MCP_READ_STATUS 0xA0
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#define MCP_RX_STATUS 0xB0
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#define MCP_RESET 0xC0
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// CANCTRL Register Values
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#define MODE_NORMAL 0x00
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#define MODE_SLEEP 0x20
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#define MODE_LOOPBACK 0x40
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#define MODE_LISTENONLY 0x60
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#define MODE_CONFIG 0x80
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#define MODE_POWERUP 0xE0
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#define MODE_MASK 0xE0
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#define ABORT_TX 0x10
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#define MODE_ONESHOT 0x08
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#define CLKOUT_ENABLE 0x04
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#define CLKOUT_DISABLE 0x00
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#define CLKOUT_PS1 0x00
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#define CLKOUT_PS2 0x01
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#define CLKOUT_PS4 0x02
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#define CLKOUT_PS8 0x03
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// CNF1 Register Values
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#define SJW1 0x00
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#define SJW2 0x40
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#define SJW3 0x80
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#define SJW4 0xC0
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// CNF2 Register Values
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#define BTLMODE 0x80
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#define SAMPLE_1X 0x00
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#define SAMPLE_3X 0x40
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// CNF3 Register Values
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#define SOF_ENABLE 0x80
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#define SOF_DISABLE 0x00
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#define WAKFIL_ENABLE 0x40
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#define WAKFIL_DISABLE 0x00
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// CANINTF Register Bits
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#define MCP_RX0IF 0x01
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#define MCP_RX1IF 0x02
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#define MCP_TX0IF 0x04
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#define MCP_TX1IF 0x08
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#define MCP_TX2IF 0x10
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#define MCP_ERRIF 0x20
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#define MCP_WAKIF 0x40
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#define MCP_MERRF 0x80
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// BFPCTRL Register Bits
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#define B1BFS 0x20
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#define B0BFS 0x10
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#define B1BFE 0x08
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#define B0BFE 0x04
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#define B1BFM 0x02
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#define B0BFM 0x01
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// TXRTCTRL Register Bits
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#define B2RTS 0x20
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#define B1RTS 0x10
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#define B0RTS 0x08
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#define B2RTSM 0x04
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#define B1RTSM 0x02
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#define B0RTSM 0x01
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// clock
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#define MCP_16MHz 1
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#define MCP_8MHz 2
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// speed 16M
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#define MCP_16MHz_1000kBPS_CFG1 (0x00)
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#define MCP_16MHz_1000kBPS_CFG2 (0xD0)
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#define MCP_16MHz_1000kBPS_CFG3 (0x82)
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#define MCP_16MHz_500kBPS_CFG1 (0x00)
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#define MCP_16MHz_500kBPS_CFG2 (0xF0)
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#define MCP_16MHz_500kBPS_CFG3 (0x86)
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#define MCP_16MHz_250kBPS_CFG1 (0x41)
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#define MCP_16MHz_250kBPS_CFG2 (0xF1)
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#define MCP_16MHz_250kBPS_CFG3 (0x85)
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#define MCP_16MHz_200kBPS_CFG1 (0x01)
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#define MCP_16MHz_200kBPS_CFG2 (0xFA)
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#define MCP_16MHz_200kBPS_CFG3 (0x87)
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#define MCP_16MHz_125kBPS_CFG1 (0x03)
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#define MCP_16MHz_125kBPS_CFG2 (0xF0)
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#define MCP_16MHz_125kBPS_CFG3 (0x86)
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#define MCP_16MHz_100kBPS_CFG1 (0x03)
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#define MCP_16MHz_100kBPS_CFG2 (0xFA)
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#define MCP_16MHz_100kBPS_CFG3 (0x87)
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#define MCP_16MHz_95kBPS_CFG1 (0x03)
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#define MCP_16MHz_95kBPS_CFG2 (0xAD)
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#define MCP_16MHz_95kBPS_CFG3 (0x07)
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#define MCP_16MHz_83k3BPS_CFG1 (0x03)
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#define MCP_16MHz_83k3BPS_CFG2 (0xBE)
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#define MCP_16MHz_83k3BPS_CFG3 (0x07)
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#define MCP_16MHz_80kBPS_CFG1 (0x03)
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#define MCP_16MHz_80kBPS_CFG2 (0xFF)
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#define MCP_16MHz_80kBPS_CFG3 (0x87)
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#define MCP_16MHz_50kBPS_CFG1 (0x07)
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#define MCP_16MHz_50kBPS_CFG2 (0xFA)
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#define MCP_16MHz_50kBPS_CFG3 (0x87)
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#define MCP_16MHz_40kBPS_CFG1 (0x07)
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#define MCP_16MHz_40kBPS_CFG2 (0xFF)
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#define MCP_16MHz_40kBPS_CFG3 (0x87)
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#define MCP_16MHz_33kBPS_CFG1 (0x09)
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#define MCP_16MHz_33kBPS_CFG2 (0xBE)
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#define MCP_16MHz_33kBPS_CFG3 (0x07)
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#define MCP_16MHz_31k25BPS_CFG1 (0x0F)
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#define MCP_16MHz_31k25BPS_CFG2 (0xF1)
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#define MCP_16MHz_31k25BPS_CFG3 (0x85)
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#define MCP_16MHz_25kBPS_CFG1 (0X0F)
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#define MCP_16MHz_25kBPS_CFG2 (0XBA)
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#define MCP_16MHz_25kBPS_CFG3 (0X07)
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#define MCP_16MHz_20kBPS_CFG1 (0x0F)
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#define MCP_16MHz_20kBPS_CFG2 (0xFF)
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#define MCP_16MHz_20kBPS_CFG3 (0x87)
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#define MCP_16MHz_10kBPS_CFG1 (0x1F)
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#define MCP_16MHz_10kBPS_CFG2 (0xFF)
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#define MCP_16MHz_10kBPS_CFG3 (0x87)
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#define MCP_16MHz_5kBPS_CFG1 (0x3F)
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#define MCP_16MHz_5kBPS_CFG2 (0xFF)
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#define MCP_16MHz_5kBPS_CFG3 (0x87)
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#define MCP_16MHz_666kBPS_CFG1 (0x00)
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#define MCP_16MHz_666kBPS_CFG2 (0xA0)
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#define MCP_16MHz_666kBPS_CFG3 (0x04)
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// speed 8M
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#define MCP_8MHz_1000kBPS_CFG1 (0x00)
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#define MCP_8MHz_1000kBPS_CFG2 (0x80)
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#define MCP_8MHz_1000kBPS_CFG3 (0x00)
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#define MCP_8MHz_500kBPS_CFG1 (0x00)
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#define MCP_8MHz_500kBPS_CFG2 (0x90)
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#define MCP_8MHz_500kBPS_CFG3 (0x02)
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#define MCP_8MHz_250kBPS_CFG1 (0x00)
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#define MCP_8MHz_250kBPS_CFG2 (0xb1)
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#define MCP_8MHz_250kBPS_CFG3 (0x05)
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#define MCP_8MHz_200kBPS_CFG1 (0x00)
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#define MCP_8MHz_200kBPS_CFG2 (0xb4)
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#define MCP_8MHz_200kBPS_CFG3 (0x06)
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#define MCP_8MHz_125kBPS_CFG1 (0x01)
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#define MCP_8MHz_125kBPS_CFG2 (0xb1)
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#define MCP_8MHz_125kBPS_CFG3 (0x05)
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#define MCP_8MHz_100kBPS_CFG1 (0x01)
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#define MCP_8MHz_100kBPS_CFG2 (0xb4)
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#define MCP_8MHz_100kBPS_CFG3 (0x06)
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#define MCP_8MHz_80kBPS_CFG1 (0x01)
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#define MCP_8MHz_80kBPS_CFG2 (0xbf)
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#define MCP_8MHz_80kBPS_CFG3 (0x07)
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#define MCP_8MHz_50kBPS_CFG1 (0x03)
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#define MCP_8MHz_50kBPS_CFG2 (0xb4)
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#define MCP_8MHz_50kBPS_CFG3 (0x06)
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#define MCP_8MHz_40kBPS_CFG1 (0x03)
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#define MCP_8MHz_40kBPS_CFG2 (0xbf)
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#define MCP_8MHz_40kBPS_CFG3 (0x07)
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#define MCP_8MHz_31k25BPS_CFG1 (0x07)
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#define MCP_8MHz_31k25BPS_CFG2 (0xa4)
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#define MCP_8MHz_31k25BPS_CFG3 (0x04)
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#define MCP_8MHz_20kBPS_CFG1 (0x07)
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#define MCP_8MHz_20kBPS_CFG2 (0xbf)
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#define MCP_8MHz_20kBPS_CFG3 (0x07)
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#define MCP_8MHz_10kBPS_CFG1 (0x0f)
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#define MCP_8MHz_10kBPS_CFG2 (0xbf)
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#define MCP_8MHz_10kBPS_CFG3 (0x07)
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#define MCP_8MHz_5kBPS_CFG1 (0x1f)
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#define MCP_8MHz_5kBPS_CFG2 (0xbf)
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#define MCP_8MHz_5kBPS_CFG3 (0x07)
|
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|
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|
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#define MCPDEBUG (0)
|
||
|
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#define MCPDEBUG_TXBUF (0)
|
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|
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#define MCP_N_TXBUFFERS (3)
|
||
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|
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|
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#define MCP_RXBUF_0 (MCP_RXB0SIDH)
|
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|
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#define MCP_RXBUF_1 (MCP_RXB1SIDH)
|
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|
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|
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#define MCP2515_SELECT() digitalWrite(SPICS, LOW)
|
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|
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#define MCP2515_UNSELECT() digitalWrite(SPICS, HIGH)
|
||
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|
||
|
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#define MCP2515_OK (0)
|
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|
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#define MCP2515_FAIL (1)
|
||
|
|
#define MCP_ALLTXBUSY (2)
|
||
|
|
|
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|
|
#define CANDEBUG 1
|
||
|
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|
||
|
|
#define CANUSELOOP 0
|
||
|
|
|
||
|
|
#define CANSENDTIMEOUT (200) // milliseconds
|
||
|
|
|
||
|
|
#define MCP_PIN_HIZ (0)
|
||
|
|
#define MCP_PIN_INT (1)
|
||
|
|
#define MCP_PIN_OUT (2)
|
||
|
|
#define MCP_PIN_IN (3)
|
||
|
|
|
||
|
|
#define MCP_RX0BF (0)
|
||
|
|
#define MCP_RX1BF (1)
|
||
|
|
#define MCP_TX0RTS (2)
|
||
|
|
#define MCP_TX1RTS (3)
|
||
|
|
#define MCP_TX2RTS (4)
|
||
|
|
|
||
|
|
|
||
|
|
// initial value of gCANAutoProcess
|
||
|
|
|
||
|
|
#define CANAUTOPROCESS (1)
|
||
|
|
#define CANAUTOON (1)
|
||
|
|
#define CANAUTOOFF (0)
|
||
|
|
#define CAN_STDID (0)
|
||
|
|
#define CAN_EXTID (1)
|
||
|
|
#define CANDEFAULTIDENT (0x55CC)
|
||
|
|
#define CANDEFAULTIDENTEXT (CAN_EXTID)
|
||
|
|
|
||
|
|
|
||
|
|
typedef enum {
|
||
|
|
CAN_NOBPS,
|
||
|
|
CAN_5KBPS,
|
||
|
|
CAN_10KBPS,
|
||
|
|
CAN_20KBPS,
|
||
|
|
CAN_25KBPS,
|
||
|
|
CAN_31K25BPS,
|
||
|
|
CAN_33KBPS ,
|
||
|
|
CAN_40KBPS ,
|
||
|
|
CAN_50KBPS ,
|
||
|
|
CAN_80KBPS ,
|
||
|
|
CAN_83K3BPS ,
|
||
|
|
CAN_95KBPS ,
|
||
|
|
CAN_100KBPS ,
|
||
|
|
CAN_125KBPS ,
|
||
|
|
CAN_200KBPS ,
|
||
|
|
CAN_250KBPS ,
|
||
|
|
CAN_500KBPS ,
|
||
|
|
CAN_666KBPS ,
|
||
|
|
CAN_1000KBPS
|
||
|
|
} MCP2515_BITTIME_SETUP;
|
||
|
|
|
||
|
|
#define CAN_OK (0)
|
||
|
|
#define CAN_FAILINIT (1)
|
||
|
|
#define CAN_FAILTX (2)
|
||
|
|
#define CAN_MSGAVAIL (3)
|
||
|
|
#define CAN_NOMSG (4)
|
||
|
|
#define CAN_CTRLERROR (5)
|
||
|
|
#define CAN_GETTXBFTIMEOUT (6)
|
||
|
|
#define CAN_SENDMSGTIMEOUT (7)
|
||
|
|
#define CAN_FAIL (0xff)
|
||
|
|
|
||
|
|
|
||
|
|
// #define CAN_OK (0)
|
||
|
|
// #define CAN_FAILINIT (1)
|
||
|
|
// #define CAN_FAILTX (2)
|
||
|
|
// #define CAN_MSGAVAIL (3)
|
||
|
|
#define CAN_NOMSG (4)
|
||
|
|
#define CAN_CTRLERROR (5)
|
||
|
|
#define CAN_GETTXBFTIMEOUT (6)
|
||
|
|
#define CAN_SENDMSGTIMEOUT (7)
|
||
|
|
#define CAN_FAIL (0xff)
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
#define CAN_MAX_CHAR_IN_MESSAGE (8)
|
||
|
|
|
||
|
|
#endif
|
||
|
|
/*********************************************************************************************************
|
||
|
|
END FILE
|
||
|
|
*********************************************************************************************************/
|